Sub-threshold leakage current in a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistors) is the drain-to-source current present when the gate-to-source voltage of the MOSFET is zero. As CMOS process technology scales to smaller dimensions, the sub-threshold leakage current density in a transistor increases. Unless properly addressed, this increase may lead to a relatively substantial amount of wasted power in various functional units of a computer system, such as register files or caches. For example, consider a computer system, such as that illustrated in FIG. 1. In FIG. 1, die 102 comprises a microprocessor with many sub-blocks, such as arithmetic logic unit (ALU) 104, register file 105, and on-die cache 106. Die 102 may also communicate to other levels of cache, such as off-die cache 108. Higher memory hierarchy levels, such as system memory 110, are accessed via host bus 112 and chipset 114. In addition, other functional units not on die 102, such as graphics accelerator 116 and network interface controller (NIC) 118, to name just a few, may communicate with die 102 via appropriate busses or ports. Each of these functional units may physical reside on one die or more than one dice. Some or parts of more than one functional unit may reside on the same die.
Sub-threshold leakage current in register file 105 or cache 106 may represent a substantial amount of wasted power in those functional units. It is desirable for such functional units to be modified to reduce sub-threshold leakage current with minimal increase in circuit complexity.